A semiconductor device having p-channel type and n-channel type thin film transistors (TFTs) formed on the same substrate, and an electronic device equipped with such a semiconductor device have been developed (Patent Documents 1 and 2, for example).
In an active matrix liquid crystal display device or an organic EL display device, for example, a technique for integrally forming a driver circuit on an active matrix substrate has been proposed. A typical driver circuit uses a CMOS (Complementary Metal Oxide Semiconductor) that includes a p-channel type TFT (abbreviated to “p-type TFT” below) and an n-channel type TFT (abbreviated to “n-type TFT” below). In order to prevent an occurrence of a leak current in the configuration using the CMOS, driving voltages of the respective TFTs need to be adjusted such that the two types of TFTs, which constitute the CMOS, are both turned off when the gate voltage is not applied. Also, from the perspective of reducing power consumption, a reduction in driving voltages of the TFTs is sought after.
In an active matrix liquid crystal display device or an organic EL display device, a technique for providing a memory circuit in each pixel on the active matrix substrate has also been proposed (Patent Document 1 and the like). With this configuration, image data of each pixel can be stored in the memory circuit (referred to as “image memory” below) provided in the pixel, which makes it possible to continuously display a still image without receiving a supply of image data from the outside, thereby reducing the power consumption for image display.
For the image memory, the use of a DRAM (Dynamic Random Access Memory) or an SRAM (Static Random Access Memory) has been proposed. Between the two, the SRAM is able to operate faster than the DRAM, and because there is no need to perform a refresh operation, which is required in the DRAM, the power consumption can be reduced in the SRAM. The SRAM has a flip-flop circuit that uses a plurality of TFTs including p-type and n-type TFTs. Even if a display device is provided with such image memories, a further reduction in driving voltages may be needed, depending on applications in which the display device is used.
In order to further reduce a driving voltage in the above-mentioned display device, which is equipped with both the p-type and n-type TFTs, it is necessary to minimize respective threshold voltages Vth of the p-type TFT and the n-type TFT.
However, between the p-type TFT and the n-type TFT, the respective voltage-current characteristics (Vg-Id characteristics) differ (see FIG. 18, for example). Therefore, it is difficult to set the value of the threshold voltage Vth such that both TFTs are turned off when the gate voltage Vg is 0V (i.e., normally off). The reason for this will be described in detail below.
A typical semiconductor layer in a TFT is patterned to have a slanted portion (tapered portion) on the periphery thereof, and in the semiconductor layer, the threshold voltage Vth differs between the slanted portion and a planarized portion that has a flat surface. Specifically, as shown in FIG. 13, in both the n-type TFT and the p-type TFT, the voltage-current curve of the slanted portion is shifted to the lower voltage side as compared with the voltage-current curve of the planarized portion. This phenomenon is presumably caused by damage given to the slanted portion of the semiconductor layer during an etching process or an ashing process of the semiconductor film (silicon film).
FIGS. 14(a) and 14(b) are graphs that respectively show examples of the voltage-current characteristics of the n-type TFT and the p-type TFT. The voltage-current characteristics of the respective TFTs are indicated by the solid lines. The voltage-current characteristics of the planarized portion and the slanted portion are indicated by the dashed lines. As shown in the figures, the voltage-current characteristics of each TFT are represented by a curve that is obtained by combining the voltage-current curve of the planarized portion and the voltage-current curve of the slanted portion. FIG. 15 is a plan view of the n-type TFT, schematically showing a path in which the drain current flows. FIG. 16 is a diagram for illustrating an adjustment of the threshold voltage Vth in the n-type TFT.
As shown in FIG. 14(a), in the voltage-current characteristics of the n-type TFT, the drain current Id changes in two steps upon driving up with an increase in the gate voltage Vg. (So-called “hump” appears.) This is because the drain current Id (e) (see FIG. 15) that flows through the slanted portion of the semiconductor layer 11 starts increasing at a lower voltage Vg(e), and the drain current Id(m) (see FIG. 15) that flows through the planarized portion of the semiconductor layer 11 starts increasing at a voltage Vg(m) that is higher than Vg(e). That is, the slanted portion of the semiconductor layer 11 functions as a parasitic transistor, and the characteristics thereof largely affect the voltage-current characteristic of the entire n-type TFT.
As shown in FIG. 16, in the n-type TFT, when a p-type impurity is doped (channel-doped) into the semiconductor layer thereof, for example, the voltage-current curve of the n-type TFT can be shifted to the higher voltage side. Therefore, it is possible to make an adjustment such that the drain current Id becomes the smallest (off state) when the gate voltage Vg is 0V. However, when such an adjustment is made, the threshold voltage Vth is also shifted to the higher voltage side, and therefore, it is not possible to maintain the threshold voltage Vth at a low level.
On the other hand, in the p-type TFT, as shown in FIG. 14(b), the drain current Id(m) (see FIG. 15) that flows through the planarized portion starts increasing at a voltage Vg(m), and the drain current Id(e) (see FIG. 15) that flows through the slanted portion starts increasing at the voltage Vg(e) (Vg(m)>Vg(e)). The drain current Id(e) that flows through the slanted portion is significantly smaller than the drain current Id(m) that flows through the planarized portion. Therefore, in the p-type TFT, the characteristics of the parasitic transistor in the slanted portion are covered by the characteristics of the planarized portion, and are therefore not shown. Thus, in the p-type TFT, even when an adjustment is made such that the drain current Id becomes the smallest (off state) when the gate voltage Vg is 0V by introducing a p-type impurity into the channel region of the semiconductor layer, the threshold voltage Vth can be kept at a low level.
As described above, in the p-type TFT, it is possible to make an adjustment such that the TFT is turned off when the gate voltage Vg is 0V, while maintaining the threshold voltage Vth at a low level. However, in the n-type TFT, it is difficult to do so because of the characteristics of the parasitic transistor in the n-type TFT.
To solve this problem, Patent Document 1 discloses a technique of introducing a p-type impurity into the slanted portion of the semiconductor layer of the n-type TFT at a higher concentration than that in the planarized portion thereof. This makes it possible to move the voltage-current curve of the parasitic transistor of the slanted portion so as to be masked by the voltage-current curve of the planarized portion.
FIGS. 17(a) and 17(b) respectively show cross-sectional views for explaining a method of manufacturing the n-type TFT and the p-type TFT disclosed in Patent Document 1. FIG. 17(a) is a cross-sectional view of the semiconductor layer of the n-type TFT, and FIG. 17(b) is a cross-sectional view of the semiconductor layer of the p-type TFT. Below, with reference to FIG. 17, the method disclosed in Patent Document 1 will be explained.
First, on a substrate 241, a base insulating film 242 is formed, and after forming a semiconductor film thereon, the semiconductor film is doped with a p-type impurity (boron). Next, on the semiconductor film, a mask film made of a silicon oxide film, for example, is formed. Next, in an n-type TFT forming region and a p-type TFT forming region on the substrate 241, resist films that cover parts of the mask film are respectively formed. Thereafter, using the resist films as masks, the semiconductor film and the mask film are etched into island shapes.
This way, as shown in FIG. 17, island-shaped semiconductor layer 243n and mask layer 244n are formed in the n-type TFT forming region, and island-shaped semiconductor layer 243p and mask layer 244p are formed in the p-type TFT forming region. In this etching, the edge portions of the resist films in the respective TFT forming regions gradually recede. Along with this, portions of the semiconductor films that are protruding from the resist films and the mask layers 244n and 244p are etched so as to be thinner as they go further from the edge portions of the mask layers 244n and 244p. As a result, slanted portions are formed in the peripheries of the semiconductor layers 243n and 243p. 
As shown in FIGS. 17(a) and 17(b), after removing the resist films, a resist film R4 is formed to cover the semiconductor layer 243p in the p-type TFT forming region, but not to cover the semiconductor layer 243n in the n-type TFT forming region.
Next, a p-type impurity that is set so as to pass through the mask layer 244n is implanted into the entire semiconductor layer 243n. Subsequently, a p-type impurity that is set so as not to pass through the mask layer 244n is selectively implanted into a portion not covered by the mask layer 244n, which is the slanted portion of the semiconductor layer 243n. This way, the slanted portion of the semiconductor layer 243n is doped with twice to five times as much p-type impurity as that in the planarized portion in volume density. As described, in the n-type TFT, by introducing a p-type impurity into the slanted portion at a higher concentration than that in the planarized portion, the voltage-current curve of the parasitic transistor of the slanted portion can be shifted to the higher voltage side, thereby suppressing the effect of the parasitic transistor of the slanted portion of the semiconductor layer 243n. 
Next, the resist film R4 is removed, and thereafter, an insulating film and a gate electrode (not shown) are formed on the mask layers 244n and 244p. The mask layers 244n and 244p and the insulating film are used as a gate insulating film.